569 lines
38 KiB
Plaintext
569 lines
38 KiB
Plaintext
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MFD-0816 TECHNICAL SPECIFACTION & OVERVIEW
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November 2024
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CONTENTS
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────────────────────────────────────────────────────────────────────────────────
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1..... INTRODUCTION & OVERVIEW
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1.1... PINS
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2..... REGISTERS
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2.1... GENERAL PURPOSE REGISTERS
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2.2... SPECIALIZED REGISTERS
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2.2.1. THE STACK
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2.2.2. FLAGS
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3..... ADDRESSING & THE I/O BUS
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3.1... I/O BUS INSTRUCTIONS
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4..... INSTRUCTION SET OVERVIEW
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4.1... INSTRUCTION ENCODING
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4.1.1. REGISTER IDENTIFICATION
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5..... ADDRESSING MODES
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6..... INTERRUPTS
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6.1... HARDWARE INTERRUPTS
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6.2... SOFTWARE INTERRUPTS
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7..... RESET
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...... LICENSE
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1. INTRODUCTION & OVERVIEW
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────────────────────────────────────────────────────────────────────────────────
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The MFD-0816 is a 16-bit fantasy CPU and based on the intel 8088.
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► 16-bit address bus
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► 16-bit word
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► 8-bit I/O bus
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► 4x 16-bit general purpose register
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1.1. PINS
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────────────────────────────────────────────────────────────────────────────────
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┌───────┬────────┬────────────────────────────────────────────────┐
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│ NAME │ PINS │ DESCRIPTION │
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├───────┼────────┼────────────────────────────────────────────────┤
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│ CLK │ 00 │ Clock pin. When high the CPU executes one step │
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├───────┼────────┼────────────────────────────────────────────────┤
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│ AIO │ 01..16 │ 16-bit Memory IO Bus │
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├───────┼────────┼────────────────────────────────────────────────┤
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│ GIO │ 17..24 │ 8-bit IO Bus │
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├───────┼────────┼────────────────────────────────────────────────┤
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│ IRQ │ 25 │ Interrupt Request │
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├───────┼────────┼────────────────────────────────────────────────┤
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│ IRA │ 26 │ Interrupt Acknowledge │
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├───────┼────────┼────────────────────────────────────────────────┤
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│ RESET │ 27 │ Reset │
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├───────┼────────┼────────────────────────────────────────────────┤
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│ AMS │ 28 │ Memory IO Bus Mode Select │
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├───────┼────────┼────────────────────────────────────────────────┤
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│ GMS │ 29 │ 8-bit IO Bus Mode Select │
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└───────┴────────┴────────────────────────────────────────────────┘
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2. REGISTERS
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2.1. GENERAL PURPOSE REGISTERS
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────────────────────────────────────────────────────────────────────────────────
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The MFD-0816 has 4 16-bit general purpose registers with the following names:
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► ACL (AH & AL)
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► BCL (BH & BL)
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► CCL (CH & CL)
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► DCL (DH & DL)
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Each general purpose register of the MFD-0816 is usable as either a complete
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WORD or as its high and low bytes.
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┌─────────┐
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│ ACL │
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├────┬────┤
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│ AH │ AL │
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└────┴────┘
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The above illustration shows the register "ACL", which can be used as a
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complete word with this name, alternatively its high byte can be accessed
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with the "AH" name and the low byte using "AL".
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2.2. SPECIALIZED REGISTERS
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────────────────────────────────────────────────────────────────────────────────
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The MFD-0816 has the following specialized registers:
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► SP (Stack Pointer)
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► IP (Instruction Pointer)
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► AR (Accumulator)
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► FL (Flags)
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► IID (Interrupt ID)
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All of these registers have a size of one word.
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The Stack Pointer register holds the current address of the top of the stack.
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The Instruction Pointer register holds the address of the
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current instruction.
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The Accumulator register holds the result of the last arithmetic operation
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The Flags register holds an assortment of different bit flags, elaborated
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upon in chapter 2.2.2. Bits can only be set by their respective clear and set
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instructions.
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The IID register hold the value of the last interrupt. It can only be set
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via an interrupt.
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2.2.1. THE STACK
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────────────────────────────────────────────────────────────────────────────────
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The stack is a memory structure where the first element "pushed" on to it will
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be the last element to leave it. In the case of the MFD-0816, one
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stack-element is a word.
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In the case of this CPU, the stack grows "downwards" (the address of the top
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of the stack gets smaller the larger it gets). This address is held in the
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SP register. In case the value of SP is equal to 0 and another element is
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"pushed" onto the stack it will cause a CPU exception to be thrown.
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The starting location of the stack is not fixed and must be set when
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initializing the CPU. This is simply done by loading the SP register with the
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address where the stack should start. Note that this address must always be a
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multiple of two.
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2.2.2. FLAGS
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────────────────────────────────────────────────────────────────────────────────
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┌──────┬────┬────┬────┬────┬────┬────┬────┬────┬────┬────┬────┬────┬────┐
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│ BIT │ 0F │ 0E │ 0D │ 0C │ 0B │ 0A │ 09 │ 08 │ 07 │ 06 │ 05 │ 04 │ 03 │
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├──────┼────┼────┼────┼────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤
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│ NAME │ OF │ CF │ ZF │ NF │ IE │ RT │ RS │ RS │ RS │ RS │ RS │ RS │ RS │
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└──────┴────┴────┴────┴────┴────┴────┴────┴────┴────┴────┴────┴────┴────┘
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┌──────┬────┬────┬────┐
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│ BIT │ 02 │ 01 │ 00 │
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├──────┼────┼────┼────┤
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│ NAME │ RS │ RS │ RS │
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└──────┴────┴────┴────┘
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► OF (Overflow Flag) Set if the last arithmetic operation overflowed.
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► CF (Carry Flag) Set to indicate that an arithmetic carry
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has been generated.
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► ZF (Zero Flag) Set to indicate that the last arithmetic operation
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resulted in a value equal to 0 in the
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accumulator register.
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► NF (Negative Flag) Set if the result of the last arithmetic operation has
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its highest (left most) bit set.
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► IE (Interrupt Enable) If set, interrupts are enabled and will be handled.
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► RT (Reset) If set, the processor is in the reset process.
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► RS (Reserved) Bits marked with this name are reserved for
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future use.
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3. ADDRESSING & THE I/O BUS
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────────────────────────────────────────────────────────────────────────────────
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The MFD-0816 provides a regular address & data bus mainly used for
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loading of instructions and memory. The address bus and its corresponding
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data bus are both 16-bits wide. The high-byte of the received data may be
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ignored by the CPU if not needed.
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Write Operation:
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T1 ╷ T2 ╷
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CLK ┌──────────────────┐ ┌────────────────────┐
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──┘ └────────────────────┘ └─
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AMS ┌────────────────────┐
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┘ └───────────────────────────────────────────
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🮣───────────────────🮢 🮣────────────────────🮢
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AIO ─🮤 ADDRESS OUT 🮥────────────────────🮤 DATA OUT 🮥─
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🮡───────────────────🮠 🮡────────────────────🮠
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Read Operation:
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T1 ╷ T2 ╷
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CLK ┌──────────────────┐ ┌────────────────────┐
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──┘ └──────────────────┘ └─
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AMS ┌────────────────────────────────────────────────────────────┐
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┘ └─
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🮣───────────────────🮢 🮣────────────────────🮢
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AIO ─🮤 ADDRESS OUT 🮥──────────────────🮤 DATA IN 🮥─
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🮡───────────────────🮠 🮡────────────────────🮠
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► If AMS is high during T1, the operation is a write opeartion. If AMS is
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also hgih during T2, it is a read operation.
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► During T1 the 16-bit address is set.
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► (Write Operation) During T2 the word to be written is set in case of
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a write operation.
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► (Write Operation) During T2 the requested data must be set by the peer.
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An 8-bit I/O bus is also provided for interacting with external hardware
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without requiring memory-mapping.
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Write Operation:
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T1 ╷ T2 ╷ T3 ╷ T4 ╷
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CLK ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐
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─┘ └──────┘ └──────┘ └──────┘ └─
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GMS ┌─────────────────────┐
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┘ └─────────────────────────────
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🮣────────────────────🮢 🮣────────────────────🮢
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GIO ─🮤 ADDRESS OUT 🮥──────🮤 DATA OUT 🮥─
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🮡────────────────────🮠 🮡────────────────────🮠
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Read Operation:
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T1 ╷ T2 ╷ T3 ╷ T4 ╷
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CLK ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐
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─┘ └──────┘ └──────┘ └──────┘ └─
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GMS
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────────────────────────────────────────────────────
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🮣────────────────────🮢 🮣────────────────────🮢
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GIO ─🮤 ADDRESS OUT 🮥──────🮤 DATA IN 🮥─
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🮡────────────────────🮠 🮡────────────────────🮠
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► If GMS is high only during T1, the operation is a write opeartion.
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If it is also high during T2, it is a read operation.
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► During T1 the high-byte of the 16-bit address is set.
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► During T2 the low-byte of the 16-bit address is set.
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► (Write Operation) During T3 the high-byte of the word is set.
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► (Write Operation) During T4 the low-byte of the word is set.
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► (Read Operation) During T3 the high-byte of the word
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must be set by the peer.
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► (Read Operation) During T4 the low-byte of the word
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must be set by the peer.
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3.1. I/O BUS INSTRUCTIONS
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────────────────────────────────────────────────────────────────────────────────
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Four instructions for operation on the I/O BUS are provided:
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► OUT - Write data to the bus
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► IN - Read data from the bus
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► BOT - Write a block of data to the bus
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► BIN - Read a block of data from the bus
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4. INSTRUCTION SET OVERVIEW
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────────────────────────────────────────────────────────────────────────────────
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┌──────┬──────────────────────────────────┬────────────┐
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│ NAME │ MEANING │ OPCODE(S) │
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├──────┼──────────────────────────────────┼────────────┤
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│ ADC │ Add with carry │ 0x00 │
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├──────┼──────────────────────────────────┼────────────┤
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│ ADD │ Add │ 0x01 │
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├──────┼──────────────────────────────────┼────────────┤
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│ AND │ Logical AND │ 0x02 │
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├──────┼──────────────────────────────────┼────────────┤
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│ BIN │ Read block of data from I/O │ 0x03 │
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├──────┼──────────────────────────────────┼────────────┤
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│ BOT │ Write block of data to I/O │ 0x04 │
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├──────┼──────────────────────────────────┼────────────┤
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│ CALL │ Call subroutine │ 0x05 │
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├──────┼──────────────────────────────────┼────────────┤
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│ CLf │ Clear flag │ 0x2b..0x3a │
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├──────┼──────────────────────────────────┼────────────┤
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│ CMP │ Compare operands │ 0x07 │
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├──────┼──────────────────────────────────┼────────────┤
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│ DEC │ Decrement by 1 │ 0x08 │
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├──────┼──────────────────────────────────┼────────────┤
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│ DIV │ Unsigned divide │ 0x09 │
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├──────┼──────────────────────────────────┼────────────┤
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│ IDIV │ Signed divide │ 0x0a │
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├──────┼──────────────────────────────────┼────────────┤
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│ IMUL │ Signed multiply │ 0x0b │
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├──────┼──────────────────────────────────┼────────────┤
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│ IN │ Read data from I/O │ 0x0c │
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├──────┼──────────────────────────────────┼────────────┤
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│ INC │ Increment by 1 │ 0x0d │
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├──────┼──────────────────────────────────┼────────────┤
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│ INT │ Trigger interrupt │ 0x0e │
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├──────┼──────────────────────────────────┼────────────┤
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│ IRET │ Return from interrupt │ 0x0f │
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├──────┼──────────────────────────────────┼────────────┤
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│ Jcc │ Jump (if condition) │ 0x10..0x1a │
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├──────┼──────────────────────────────────┼────────────┤
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│ LD │ Load word to register │ 0x1b │
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├──────┼──────────────────────────────────┼────────────┤
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│ MOV │ Mov value between registers │ 0x1c │
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├──────┼──────────────────────────────────┼────────────┤
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│ MUL │ Unsigned multiply │ 0x1d │
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├──────┼──────────────────────────────────┼────────────┤
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│ NEG │ Negate │ 0x1e │
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├──────┼──────────────────────────────────┼────────────┤
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│ NOP │ No operation │ 0x1f │
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├──────┼──────────────────────────────────┼────────────┤
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│ NOT │ Negate the operand (logical NOT) │ 0x20 │
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├──────┼──────────────────────────────────┼────────────┤
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│ OR │ Logical OR │ 0x21 │
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├──────┼──────────────────────────────────┼────────────┤
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│ OUT │ Write data to I/O │ 0x22 │
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├──────┼──────────────────────────────────┼────────────┤
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│ POP │ Pop data from stack │ 0x23 │
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├──────┼──────────────────────────────────┼────────────┤
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│ PUSH │ Push data onto stack │ 0x24 │
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├──────┼──────────────────────────────────┼────────────┤
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│ RET │ Return from subroutine │ 0x25 │
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├──────┼──────────────────────────────────┼────────────┤
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│ ROL │ Rotate left │ 0x26 │
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├──────┼──────────────────────────────────┼────────────┤
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│ ROR │ Roate right │ 0x27 │
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├──────┼──────────────────────────────────┼────────────┤
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│ SL │ Shift left │ 0x28 │
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├──────┼──────────────────────────────────┼────────────┤
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│ SR │ Shift right │ 0x29 │
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├──────┼──────────────────────────────────┼────────────┤
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│ ST │ Store word from register │ 0x2a │
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├──────┼──────────────────────────────────┼────────────┤
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│ STf │ Set flag │ 0x3b..0x4a │
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├──────┼──────────────────────────────────┼────────────┤
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│ SUB │ Subtraction │ 0x4b │
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├──────┼──────────────────────────────────┼────────────┤
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│ TEST │ Logical compare (AND) │ 0x4c │
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├──────┼──────────────────────────────────┼────────────┤
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│ XOR │ Exclusive OR │ 0x4d │
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└──────┴──────────────────────────────────┴────────────┘
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4.1 INSTRUCTION ENCODING
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────────────────────────────────────────────────────────────────────────────────
|
||
|
|
|
||
|
|
┌────────┬────────┬───────────────────────────────────────────┐
|
||
|
|
│ WORD │ BITS │ USAGE │
|
||
|
|
├────────┼────────┼───────────────────────────────────────────┤
|
||
|
|
│ 00 │ 0F..08 │ Identification of the instruction │
|
||
|
|
├────────┼────────┼───────────────────────────────────────────┤
|
||
|
|
│ 00 │ 07..04 │ Operand 1 addressing mode │
|
||
|
|
├────────┼────────┼───────────────────────────────────────────┤
|
||
|
|
│ 00 │ 03..00 │ Operand 2 addressing mode │
|
||
|
|
└────────┴────────┴───────────────────────────────────────────┘
|
||
|
|
|
||
|
|
The addressing modes are encoded as follows:
|
||
|
|
|
||
|
|
┌────────┬────────────────────────────┐
|
||
|
|
│ VALUE │ MODE │
|
||
|
|
├────────┼────────────────────────────┤
|
||
|
|
│ 0000 │ Immediate │
|
||
|
|
├────────┼────────────────────────────┤
|
||
|
|
│ 0001 │ Direct │
|
||
|
|
├────────┼────────────────────────────┤
|
||
|
|
│ 0010 │ Indirect │
|
||
|
|
├────────┼────────────────────────────┤
|
||
|
|
│ 0101 │ Relative Direct │
|
||
|
|
├────────┼────────────────────────────┤
|
||
|
|
│ 0110 │ Relative Indirect │
|
||
|
|
├────────┼────────────────────────────┤
|
||
|
|
│ 1000 │ Register Immediate │
|
||
|
|
├────────┼────────────────────────────┤
|
||
|
|
│ 1001 │ Register Direct │
|
||
|
|
├────────┼────────────────────────────┤
|
||
|
|
│ 1010 │ Register Indirect │
|
||
|
|
├────────┼────────────────────────────┤
|
||
|
|
│ 1101 │ Register Relative Direct │
|
||
|
|
├────────┼────────────────────────────┤
|
||
|
|
│ 1110 │ Register Relative Indirect │
|
||
|
|
└────────┴────────────────────────────┘
|
||
|
|
|
||
|
|
The highest bit (bit 03) is reffered to as the register bit. If high,
|
||
|
|
the operand's immediate value identifies a register.
|
||
|
|
|
||
|
|
The second highest bit (bit 02) is the relative bit. If high,
|
||
|
|
the operands value is relative to the value of the IP register.
|
||
|
|
|
||
|
|
The second lowest bit (bit 01) is the indirect bit. If high,
|
||
|
|
the value behind the operand is another address which must be read from.
|
||
|
|
|
||
|
|
The lowest bit (bit 00) is the direct bit. If high,
|
||
|
|
the operand is an address pointing towards the actual value to be worked
|
||
|
|
with.
|
||
|
|
|
||
|
|
Bits 00 and 01 should not be set at the same time. Should the CPU encounter
|
||
|
|
this, an exception will be raised.
|
||
|
|
|
||
|
|
Bit 02 has no effect if neither Bit 01 or Bit 00 are high.
|
||
|
|
|
||
|
|
4.1.1. REGISTER IDENTIFICATION
|
||
|
|
────────────────────────────────────────────────────────────────────────────────
|
||
|
|
|
||
|
|
In case the register bit is set for a specific operand, the immediate value
|
||
|
|
is only one byte long. The register is encoded as follows:
|
||
|
|
|
||
|
|
┌─────┬───────┐
|
||
|
|
│ REG │ VALUE │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ AL │ 0x00 │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ AH │ 0x01 │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ ACL │ 0x02 │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ BL │ 0x03 │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ BH │ 0x04 │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ BCL │ 0x05 │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ CL │ 0x06 │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ CH │ 0x07 │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ CCL │ 0x08 │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ DL │ 0x09 │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ DH │ 0x0a │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ DCL │ 0x0b │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ SP │ 0x0c │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ IP │ 0x0d │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ AR │ 0x0e │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ FL │ 0x0f │
|
||
|
|
├─────┼───────┤
|
||
|
|
│ IID │ 0x10 │
|
||
|
|
└─────┴───────┘
|
||
|
|
|
||
|
|
5. ADDRESSING MODES
|
||
|
|
────────────────────────────────────────────────────────────────────────────────
|
||
|
|
|
||
|
|
Addressing modes define how instructions access operands. There are three
|
||
|
|
primary modes: Immediate, Direct, and Indirect.
|
||
|
|
|
||
|
|
In Immediate Addressing, the operand is either a literal value or a
|
||
|
|
register value. For example, in the instruction "MOV #64, AL", the immediate
|
||
|
|
value 64 is assigned directly to the register AL, making AL equal to 64.
|
||
|
|
|
||
|
|
┌─────────────┬─────────┐
|
||
|
|
│ INSTRUCTION │ OPERAND │
|
||
|
|
└─────────────┴─────────┘
|
||
|
|
IMMEDIATE ADDRESSING
|
||
|
|
|
||
|
|
In Direct Addressing, the operand specifies an address where the actual
|
||
|
|
value is stored. The instruction accesses the value directly from
|
||
|
|
this address.
|
||
|
|
|
||
|
|
┌─────────────┬───────────────────┐ ┌───────┐
|
||
|
|
│ INSTRUCTION │ OPERAND (ADDRESS) ├────────►│ VALUE │
|
||
|
|
└─────────────┴───────────────────┘ └───────┘
|
||
|
|
DIRECT ADDRESSING
|
||
|
|
|
||
|
|
Indirect Addressing also uses an address as the operand, but instead of
|
||
|
|
pointing directly to the value, the address points to another address
|
||
|
|
where the final value is stored. This requires an extra level of indirection.
|
||
|
|
|
||
|
|
┌─────────────┬───────────────────┐ ┌────────────────────────────┐
|
||
|
|
│ INSTRUCTION │ OPERAND (ADDRESS) ├────────►│ POINTER TO VALUE (ADDRESS) ├─┐
|
||
|
|
└─────────────┴───────────────────┘ ├────────────────────────────┤ │
|
||
|
|
INDIRECT ADDRESSING │ VALUE │◄┘
|
||
|
|
└────────────────────────────┘
|
||
|
|
|
||
|
|
Direct and Indirect modes typically use absolute addresses. However, they can
|
||
|
|
also operate in Relative Addressing mode, where the address is calculated
|
||
|
|
relative to the current value of the Instruction Pointer (IP) register.
|
||
|
|
|
||
|
|
► To reference a memory location before the current IP value,
|
||
|
|
the highest bit of the address must be set, indicating a negative offset.
|
||
|
|
|
||
|
|
6. INTERRUPTS
|
||
|
|
────────────────────────────────────────────────────────────────────────────────
|
||
|
|
|
||
|
|
Interrupts can be triggered by the INT instruction or the INT-Pin being pulled
|
||
|
|
high.
|
||
|
|
|
||
|
|
Both types of interrupts share this behaviour after acquiring the interrupt
|
||
|
|
id.
|
||
|
|
|
||
|
|
1. Save the value of the IP register to the top of the stack
|
||
|
|
2. Load the value from the interrupt vector into the IP register.
|
||
|
|
The interrupt vector is located at address 0xfffc
|
||
|
|
3. Clear the IE flag
|
||
|
|
4. Continue execution
|
||
|
|
|
||
|
|
After handling of an interrupt is done, the IRET instruction must be invoked.
|
||
|
|
This does the following:
|
||
|
|
|
||
|
|
1. Set the IE flag
|
||
|
|
2. Load the value from the top of the stack into the IP register
|
||
|
|
3. continue execution
|
||
|
|
|
||
|
|
6.1. HARDWARE INTERRUPTS
|
||
|
|
────────────────────────────────────────────────────────────────────────────────
|
||
|
|
|
||
|
|
Hardware interrupts consist of two sequences: The Interrupt request and the
|
||
|
|
Interrupt Acknowledge sequence.
|
||
|
|
|
||
|
|
Interrupt request:
|
||
|
|
|
||
|
|
T1 ╷
|
||
|
|
CLK ┐ ┌──────┐ ┌
|
||
|
|
└──────┘ └──────┘
|
||
|
|
|
||
|
|
IRQ ┌──────┐
|
||
|
|
───────┘ └───────
|
||
|
|
|
||
|
|
The CPU checks if the IRQ line is high at the ench of each clock cycle. So if
|
||
|
|
IRQ is high at the end of T1, an interrupt was requested. After this sequence,
|
||
|
|
the Acknowledge sequence is entered.
|
||
|
|
|
||
|
|
Interrupt acknowledge:
|
||
|
|
|
||
|
|
T1 ╷ T2 ╷
|
||
|
|
CLK ┐ ┌─────────┐ ┌─────────┐
|
||
|
|
└─────────┘ └─────────┘ └─
|
||
|
|
|
||
|
|
IRA ┌─────────────────────────────┐
|
||
|
|
──────────┘ └─
|
||
|
|
|
||
|
|
🮣──────────🮢
|
||
|
|
GIO ─────────────────────────────🮤 DATA IN 🮥─
|
||
|
|
🮡──────────🮠
|
||
|
|
|
||
|
|
As soon as the CPU is ready, it will set the IRA line high for two clock
|
||
|
|
pulses. During the first pulse, nothing else happens. During the second pulse
|
||
|
|
the CPU reads a byte of whatever data currently is on the I/O Bus. This data
|
||
|
|
is used as the interrupt id and written to the IID register.
|
||
|
|
|
||
|
|
After both sequences are completed, the CPU continues with the shared
|
||
|
|
behaviour specified in chapter 6.
|
||
|
|
|
||
|
|
6.1. SOFTWARE INTERRUPTS
|
||
|
|
────────────────────────────────────────────────────────────────────────────────
|
||
|
|
|
||
|
|
Software interrupts are a lot simpler. They are triggered by an INT
|
||
|
|
instruction.
|
||
|
|
|
||
|
|
When an INT instruction is encountered, the CPU first sets the IID register
|
||
|
|
to the value of the first operand of the instruction.
|
||
|
|
|
||
|
|
After this is completed, the CPU continues with the shared
|
||
|
|
behaviour specified in chapter 6.
|
||
|
|
|
||
|
|
7. RESET
|
||
|
|
────────────────────────────────────────────────────────────────────────────────
|
||
|
|
|
||
|
|
The CPU can be reset to start execution from the reset vector. The reset
|
||
|
|
vector is located at address 0xfffe.
|
||
|
|
|
||
|
|
T1 ╷ T2 ╷ T3 ╷
|
||
|
|
CLK ┐ ┌─────────┐ ┌─────────┐ ┌─────────┐
|
||
|
|
└─────────┘ └─────────┘ └─────────┘ └
|
||
|
|
|
||
|
|
RESET ┌─────────┐
|
||
|
|
──────────┘ └────────────────────────────────────────
|
||
|
|
|
||
|
|
In order to execute a reset, the RESET pin must be high at the end of a
|
||
|
|
clock pulse. If reset is high for longer than this, it will continually reset
|
||
|
|
the processor.
|
||
|
|
|
||
|
|
After a reset has been triggered, the RT flag is set and the next few cycles
|
||
|
|
are used to read the value of the reset vector into the IP register.
|
||
|
|
Afterwards, the RT flag is cleared and the processor resumes execution.
|
||
|
|
|
||
|
|
Note that resetting does not clear any registers or memories except for the
|
||
|
|
FL register. Interrupts also have no effect whilst resetting, regardless of
|
||
|
|
the state of the IE flag.
|
||
|
|
|
||
|
|
LICENSE
|
||
|
|
────────────────────────────────────────────────────────────────────────────────
|
||
|
|
|
||
|
|
MFD0816 DESIGN by Marie Eckert is licensed under CC BY-SA 4.0,
|
||
|
|
see <https://creativecommons.org/licenses/by-sa/4.0/>
|