update mf0816 desgin

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@ -1,5 +1,5 @@
MFD-0816 TECHNICAL SPECIFACTION & OVERVIEW MFD-0816 TECHNICAL SPECIFACTION & OVERVIEW
November 2024 January 2025
CONTENTS CONTENTS
──────────────────────────────────────────────────────────────────────────────── ────────────────────────────────────────────────────────────────────────────────
@ -28,6 +28,7 @@ CONTENTS
The MFD-0816 is a 16-bit fantasy CPU and based on the intel 8088. The MFD-0816 is a 16-bit fantasy CPU and based on the intel 8088.
► Big Endian
► 16-bit address bus ► 16-bit address bus
► 16-bit word ► 16-bit word
► 8-bit I/O bus ► 8-bit I/O bus
@ -39,7 +40,7 @@ CONTENTS
┌───────┬────────┬────────────────────────────────────────────────┐ ┌───────┬────────┬────────────────────────────────────────────────┐
│ NAME │ PINS │ DESCRIPTION │ │ NAME │ PINS │ DESCRIPTION │
├───────┼────────┼────────────────────────────────────────────────┤ ├───────┼────────┼────────────────────────────────────────────────┤
│ CLK │ 00 │ Clock pin. When high the CPU executes one step │ ICLK │ 00 │ Clock pin. When high the CPU executes one step │
├───────┼────────┼────────────────────────────────────────────────┤ ├───────┼────────┼────────────────────────────────────────────────┤
│ AIO │ 01..16 │ 16-bit Memory IO Bus │ │ AIO │ 01..16 │ 16-bit Memory IO Bus │
├───────┼────────┼────────────────────────────────────────────────┤ ├───────┼────────┼────────────────────────────────────────────────┤
@ -54,6 +55,8 @@ CONTENTS
│ AMS │ 28 │ Memory IO Bus Mode Select │ │ AMS │ 28 │ Memory IO Bus Mode Select │
├───────┼────────┼────────────────────────────────────────────────┤ ├───────┼────────┼────────────────────────────────────────────────┤
│ GMS │ 29 │ 8-bit IO Bus Mode Select │ │ GMS │ 29 │ 8-bit IO Bus Mode Select │
├───────┼────────┼────────────────────────────────────────────────┤
│ CLK │ 30 │ Clock for Memory IO & 8-bit IO Busses │
└───────┴────────┴────────────────────────────────────────────────┘ └───────┴────────┴────────────────────────────────────────────────┘
2. REGISTERS 2. REGISTERS
@ -156,39 +159,41 @@ CONTENTS
The MFD-0816 provides a regular address & data bus mainly used for The MFD-0816 provides a regular address & data bus mainly used for
loading of instructions and memory. The address bus and its corresponding loading of instructions and memory. The address bus and its corresponding
data bus are both 16-bits wide. The high-byte of the received data may be data bus are both 16-bits wide. The low-byte of the received data may be
ignored by the CPU if not needed. ignored by the CPU if not needed.
Write Operation: Write Operation:
T1 ╷ T2 T1 ╷ T2 ╷ T3
CLK ┌──────────────────┐ ┌────────────────────┐ CLK ┌──────────────────┐┌──────────────────┐┌──────────────────┐
──┘ └────────────────────┘ └─ ──┘ └┘ └┘ └─
AMS ────────────────────┐ AMS ────────────────────┐
└─────────────────────────────────────────── └─────────────────────────────────────────
🮣───────────────────🮢 🮣────────────────────🮢 🮣───────────────────🮢 🮣────────────────────🮢
AIO ─🮤 ADDRESS OUT 🮥────────────────────🮤 DATA OUT 🮥─ AIO ─🮤 ADDRESS OUT 🮥──────────────────🮤 DATA OUT 🮥─
🮡───────────────────🮠 🮡────────────────────🮠 🮡───────────────────🮠 🮡────────────────────🮠
Read Operation: Read Operation:
T1 ╷ T2 T1 ╷ T2 ╷ T3
CLK ┌──────────────────┐ ┌────────────────────┐ CLK ┌──────────────────┐┌──────────────────┐┌──────────────────┐
──┘ └──────────────────┘ └─ ──┘ └┘ └┘ └─
AMS ┌────────────────────────────────────────────────────────────┐ AMS ─────────────────────────────────────────┐
└─ └─────────────────────
🮣───────────────────🮢 🮣────────────────────🮢 🮣───────────────────🮢 🮣────────────────────🮢
AIO ─🮤 ADDRESS OUT 🮥──────────────────🮤 DATA IN 🮥─ AIO ─🮤 ADDRESS OUT 🮥──────────────────🮤 DATA IN 🮥─
🮡───────────────────🮠 🮡────────────────────🮠 🮡───────────────────🮠 🮡────────────────────🮠
► If AMS is high during T1, the operation is a write opeartion. If AMS is ► [Omitted from diagram] To trigger a Memory Bus operation, a priming
also hgih during T2, it is a read operation. clock-pulse where AMS is high is sent.
► If AMS is low during T2, the operation is a write opeartion. If AMS is
high during T2, it is a read operation.
► During T1 the 16-bit address is set. ► During T1 the 16-bit address is set.
► (Write Operation) During T2 the word to be written is set in case of ► (Write Operation) During T3 the word to be written is set in case of
a write operation. a write operation.
► (Write Operation) During T2 the requested data must be set by the peer. ► (Read Operation) During T3 the requested data must be set by the peer.
An 8-bit I/O bus is also provided for interacting with external hardware An 8-bit I/O bus is also provided for interacting with external hardware
@ -200,8 +205,8 @@ CONTENTS
CLK ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐ CLK ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐
─┘ └──────┘ └──────┘ └──────┘ └─ ─┘ └──────┘ └──────┘ └──────┘ └─
GMS ┌─────────────────────┐ GMS ────────┐
└───────────────────────────── └───────────────────────────────────────────
🮣────────────────────🮢 🮣────────────────────🮢 🮣────────────────────🮢 🮣────────────────────🮢
GIO ─🮤 ADDRESS OUT 🮥──────🮤 DATA OUT 🮥─ GIO ─🮤 ADDRESS OUT 🮥──────🮤 DATA OUT 🮥─
🮡────────────────────🮠 🮡────────────────────🮠 🮡────────────────────🮠 🮡────────────────────🮠
@ -212,12 +217,14 @@ CONTENTS
CLK ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐ CLK ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐
─┘ └──────┘ └──────┘ └──────┘ └─ ─┘ └──────┘ └──────┘ └──────┘ └─
GMS GMS ──────────────────────┐
──────────────────────────────────────────────────── ─────────────────────────────
🮣────────────────────🮢 🮣────────────────────🮢 🮣────────────────────🮢 🮣────────────────────🮢
GIO ─🮤 ADDRESS OUT 🮥──────🮤 DATA IN 🮥─ GIO ─🮤 ADDRESS OUT 🮥──────🮤 DATA IN 🮥─
🮡────────────────────🮠 🮡────────────────────🮠 🮡────────────────────🮠 🮡────────────────────🮠
► [Omitted from diagram] To trigger an I/O Bus operation, a priming
clock-pulse where GMS is high is sent.
► If GMS is high only during T1, the operation is a write opeartion. ► If GMS is high only during T1, the operation is a write opeartion.
If it is also high during T2, it is a read operation. If it is also high during T2, it is a read operation.
► During T1 the high-byte of the 16-bit address is set. ► During T1 the high-byte of the 16-bit address is set.
@ -492,9 +499,9 @@ CONTENTS
Interrupt request: Interrupt request:
T1 ╷ T1 ╷
CLK ┐ ┌──────┐ ┌ ICLK ┐ ┌──────┐ ┌
└──────┘ └──────┘ └──────┘ └──────┘
IRQ ┌──────┐ IRQ ┌──────┐
───────┘ └─────── ───────┘ └───────
@ -505,16 +512,16 @@ CONTENTS
Interrupt acknowledge: Interrupt acknowledge:
T1 ╷ T2 ╷ T1 ╷ T2 ╷
CLK ┐ ┌─────────┐ ┌─────────┐ ICLK ┐ ┌─────────┐ ┌─────────┐
└─────────┘ └─────────┘ └─ └─────────┘ └─────────┘ └─
IRA ┌─────────────────────────────┐ IRA ┌─────────────────────────────┐
──────────┘ └─ ──────────┘ └─
🮣──────────🮢 🮣──────────🮢
GIO ─────────────────────────────🮤 DATA IN 🮥─ GIO ─────────────────────────────🮤 DATA IN 🮥─
🮡──────────🮠 🮡──────────🮠
As soon as the CPU is ready, it will set the IRA line high for two clock As soon as the CPU is ready, it will set the IRA line high for two clock
pulses. During the first pulse, nothing else happens. During the second pulse pulses. During the first pulse, nothing else happens. During the second pulse
@ -542,12 +549,12 @@ CONTENTS
The CPU can be reset to start execution from the reset vector. The reset The CPU can be reset to start execution from the reset vector. The reset
vector is located at address 0xfffe. vector is located at address 0xfffe.
T1 ╷ T2 ╷ T3 ╷ T1 ╷ T2 ╷ T3 ╷
CLK ┐ ┌─────────┐ ┌─────────┐ ┌─────────┐ ICLK ┐ ┌─────────┐ ┌─────────┐ ┌─────────┐
└─────────┘ └─────────┘ └─────────┘ └ └─────────┘ └─────────┘ └─────────┘ └
RESET ┌─────────┐ RESET ┌─────────┐
──────────┘ └──────────────────────────────────────── ──────────┘ └────────────────────────────────────────
In order to execute a reset, the RESET pin must be high at the end of a In order to execute a reset, the RESET pin must be high at the end of a
clock pulse. If reset is high for longer than this, it will continually reset clock pulse. If reset is high for longer than this, it will continually reset