update mf0816 desgin
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MFD-0816 TECHNICAL SPECIFACTION & OVERVIEW
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MFD-0816 TECHNICAL SPECIFACTION & OVERVIEW
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November 2024
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January 2025
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CONTENTS
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CONTENTS
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────────────────────────────────────────────────────────────────────────────────
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────────────────────────────────────────────────────────────────────────────────
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@ -28,6 +28,7 @@ CONTENTS
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The MFD-0816 is a 16-bit fantasy CPU and based on the intel 8088.
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The MFD-0816 is a 16-bit fantasy CPU and based on the intel 8088.
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► Big Endian
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► 16-bit address bus
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► 16-bit address bus
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► 16-bit word
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► 16-bit word
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► 8-bit I/O bus
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► 8-bit I/O bus
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@ -39,7 +40,7 @@ CONTENTS
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┌───────┬────────┬────────────────────────────────────────────────┐
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┌───────┬────────┬────────────────────────────────────────────────┐
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│ NAME │ PINS │ DESCRIPTION │
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│ NAME │ PINS │ DESCRIPTION │
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├───────┼────────┼────────────────────────────────────────────────┤
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├───────┼────────┼────────────────────────────────────────────────┤
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│ CLK │ 00 │ Clock pin. When high the CPU executes one step │
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│ ICLK │ 00 │ Clock pin. When high the CPU executes one step │
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├───────┼────────┼────────────────────────────────────────────────┤
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├───────┼────────┼────────────────────────────────────────────────┤
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│ AIO │ 01..16 │ 16-bit Memory IO Bus │
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│ AIO │ 01..16 │ 16-bit Memory IO Bus │
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├───────┼────────┼────────────────────────────────────────────────┤
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├───────┼────────┼────────────────────────────────────────────────┤
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@ -54,6 +55,8 @@ CONTENTS
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│ AMS │ 28 │ Memory IO Bus Mode Select │
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│ AMS │ 28 │ Memory IO Bus Mode Select │
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├───────┼────────┼────────────────────────────────────────────────┤
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├───────┼────────┼────────────────────────────────────────────────┤
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│ GMS │ 29 │ 8-bit IO Bus Mode Select │
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│ GMS │ 29 │ 8-bit IO Bus Mode Select │
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├───────┼────────┼────────────────────────────────────────────────┤
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│ CLK │ 30 │ Clock for Memory IO & 8-bit IO Busses │
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└───────┴────────┴────────────────────────────────────────────────┘
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└───────┴────────┴────────────────────────────────────────────────┘
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2. REGISTERS
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2. REGISTERS
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@ -156,39 +159,41 @@ CONTENTS
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The MFD-0816 provides a regular address & data bus mainly used for
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The MFD-0816 provides a regular address & data bus mainly used for
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loading of instructions and memory. The address bus and its corresponding
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loading of instructions and memory. The address bus and its corresponding
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data bus are both 16-bits wide. The high-byte of the received data may be
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data bus are both 16-bits wide. The low-byte of the received data may be
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ignored by the CPU if not needed.
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ignored by the CPU if not needed.
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Write Operation:
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Write Operation:
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T1 ╷ T2 ╷
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T1 ╷ T2 ╷ T3 ╷
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CLK ┌──────────────────┐ ┌────────────────────┐
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CLK ┌──────────────────┐┌──────────────────┐┌──────────────────┐
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──┘ └────────────────────┘ └─
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──┘ └┘ └┘ └─
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AMS ┌────────────────────┐
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AMS ─────────────────────┐
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┘ └───────────────────────────────────────────
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└─────────────────────────────────────────
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🮣───────────────────🮢 🮣────────────────────🮢
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🮣───────────────────🮢 🮣────────────────────🮢
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AIO ─🮤 ADDRESS OUT 🮥────────────────────🮤 DATA OUT 🮥─
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AIO ─🮤 ADDRESS OUT 🮥──────────────────🮤 DATA OUT 🮥─
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🮡───────────────────🮠 🮡────────────────────🮠
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🮡───────────────────🮠 🮡────────────────────🮠
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Read Operation:
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Read Operation:
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T1 ╷ T2 ╷
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T1 ╷ T2 ╷ T3 ╷
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CLK ┌──────────────────┐ ┌────────────────────┐
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CLK ┌──────────────────┐┌──────────────────┐┌──────────────────┐
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──┘ └──────────────────┘ └─
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──┘ └┘ └┘ └─
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AMS ┌────────────────────────────────────────────────────────────┐
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AMS ─────────────────────────────────────────┐
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┘ └─
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└─────────────────────
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🮣───────────────────🮢 🮣────────────────────🮢
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🮣───────────────────🮢 🮣────────────────────🮢
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AIO ─🮤 ADDRESS OUT 🮥──────────────────🮤 DATA IN 🮥─
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AIO ─🮤 ADDRESS OUT 🮥──────────────────🮤 DATA IN 🮥─
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🮡───────────────────🮠 🮡────────────────────🮠
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🮡───────────────────🮠 🮡────────────────────🮠
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► If AMS is high during T1, the operation is a write opeartion. If AMS is
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► [Omitted from diagram] To trigger a Memory Bus operation, a priming
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also hgih during T2, it is a read operation.
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clock-pulse where AMS is high is sent.
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► If AMS is low during T2, the operation is a write opeartion. If AMS is
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high during T2, it is a read operation.
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► During T1 the 16-bit address is set.
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► During T1 the 16-bit address is set.
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► (Write Operation) During T2 the word to be written is set in case of
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► (Write Operation) During T3 the word to be written is set in case of
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a write operation.
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a write operation.
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► (Write Operation) During T2 the requested data must be set by the peer.
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► (Read Operation) During T3 the requested data must be set by the peer.
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An 8-bit I/O bus is also provided for interacting with external hardware
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An 8-bit I/O bus is also provided for interacting with external hardware
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@ -200,8 +205,8 @@ CONTENTS
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CLK ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐
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CLK ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐
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─┘ └──────┘ └──────┘ └──────┘ └─
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─┘ └──────┘ └──────┘ └──────┘ └─
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GMS ┌─────────────────────┐
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GMS ────────┐
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┘ └─────────────────────────────
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└───────────────────────────────────────────
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🮣────────────────────🮢 🮣────────────────────🮢
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🮣────────────────────🮢 🮣────────────────────🮢
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GIO ─🮤 ADDRESS OUT 🮥──────🮤 DATA OUT 🮥─
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GIO ─🮤 ADDRESS OUT 🮥──────🮤 DATA OUT 🮥─
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🮡────────────────────🮠 🮡────────────────────🮠
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🮡────────────────────🮠 🮡────────────────────🮠
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@ -212,12 +217,14 @@ CONTENTS
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CLK ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐
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CLK ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐
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─┘ └──────┘ └──────┘ └──────┘ └─
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─┘ └──────┘ └──────┘ └──────┘ └─
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GMS
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GMS ──────────────────────┐
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────────────────────────────────────────────────────
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└─────────────────────────────
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🮣────────────────────🮢 🮣────────────────────🮢
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🮣────────────────────🮢 🮣────────────────────🮢
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GIO ─🮤 ADDRESS OUT 🮥──────🮤 DATA IN 🮥─
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GIO ─🮤 ADDRESS OUT 🮥──────🮤 DATA IN 🮥─
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🮡────────────────────🮠 🮡────────────────────🮠
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🮡────────────────────🮠 🮡────────────────────🮠
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► [Omitted from diagram] To trigger an I/O Bus operation, a priming
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clock-pulse where GMS is high is sent.
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► If GMS is high only during T1, the operation is a write opeartion.
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► If GMS is high only during T1, the operation is a write opeartion.
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If it is also high during T2, it is a read operation.
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If it is also high during T2, it is a read operation.
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► During T1 the high-byte of the 16-bit address is set.
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► During T1 the high-byte of the 16-bit address is set.
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@ -492,9 +499,9 @@ CONTENTS
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Interrupt request:
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Interrupt request:
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T1 ╷
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T1 ╷
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CLK ┐ ┌──────┐ ┌
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ICLK ┐ ┌──────┐ ┌
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└──────┘ └──────┘
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└──────┘ └──────┘
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IRQ ┌──────┐
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IRQ ┌──────┐
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───────┘ └───────
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───────┘ └───────
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@ -505,16 +512,16 @@ CONTENTS
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Interrupt acknowledge:
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Interrupt acknowledge:
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T1 ╷ T2 ╷
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T1 ╷ T2 ╷
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CLK ┐ ┌─────────┐ ┌─────────┐
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ICLK ┐ ┌─────────┐ ┌─────────┐
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└─────────┘ └─────────┘ └─
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└─────────┘ └─────────┘ └─
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IRA ┌─────────────────────────────┐
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IRA ┌─────────────────────────────┐
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──────────┘ └─
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──────────┘ └─
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🮣──────────🮢
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🮣──────────🮢
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GIO ─────────────────────────────🮤 DATA IN 🮥─
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GIO ─────────────────────────────🮤 DATA IN 🮥─
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🮡──────────🮠
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🮡──────────🮠
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As soon as the CPU is ready, it will set the IRA line high for two clock
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As soon as the CPU is ready, it will set the IRA line high for two clock
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pulses. During the first pulse, nothing else happens. During the second pulse
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pulses. During the first pulse, nothing else happens. During the second pulse
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@ -542,12 +549,12 @@ CONTENTS
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The CPU can be reset to start execution from the reset vector. The reset
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The CPU can be reset to start execution from the reset vector. The reset
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vector is located at address 0xfffe.
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vector is located at address 0xfffe.
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T1 ╷ T2 ╷ T3 ╷
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T1 ╷ T2 ╷ T3 ╷
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CLK ┐ ┌─────────┐ ┌─────────┐ ┌─────────┐
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ICLK ┐ ┌─────────┐ ┌─────────┐ ┌─────────┐
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└─────────┘ └─────────┘ └─────────┘ └
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└─────────┘ └─────────┘ └─────────┘ └
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RESET ┌─────────┐
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RESET ┌─────────┐
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──────────┘ └────────────────────────────────────────
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──────────┘ └────────────────────────────────────────
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In order to execute a reset, the RESET pin must be high at the end of a
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In order to execute a reset, the RESET pin must be high at the end of a
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clock pulse. If reset is high for longer than this, it will continually reset
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clock pulse. If reset is high for longer than this, it will continually reset
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